It is desirable to operate lateral drain extended metal oxide semiconductor (MOS) transistors at increasingly higher frequencies. For example, higher operation frequencies in voltage regulators enables smaller inductors, providing reduced system costs. Operating frequency is limited by the gate-drain capacitance. It is also desirable to provide lower resistances of the lateral drain extended MOS transistors to improve power efficiency in the voltage regulators. Simultaneously attaining desired operating frequencies and resistances in lateral drain extended MOS transistors has been problematic.